The memory line in core PCE

Three lines on one chart. Look at them in order, and one of them is doing something the others are not.

Storage (PPI). Modest swings, the kind a category of enterprise drives and SSDs gives you. Five-point band for a decade. Up to +20 only now.

Software and accessories (CPI). Tracked storage all decade. Broke up to +14 in late 2025. This is the line that flows into core PCE.

Memory and loaded boards (PPI). Drifted between minus five and minus fifteen for ten years. In six months it ran to plus one hundred and fifty six. Largest move in the history of the series.

The third line is the input. The other two are what happens once the rest of the chain absorbs it.

What actually changed

Every shipped accelerator is a DRAM order. H100 is 80 GB. B200 is 192 GB. A single GB200 superchip ships with 384 GB. The three firms that make HBM (Samsung, SK Hynix, Micron) are sold out through 2026 and have committed most of 2027.

HBM uses the same wafers, same fabs, same engineers as ordinary server DRAM. Capacity that goes to HBM does not go to anything else. By Q1 2026 contract DDR5 prices were up roughly eighty percent year on year. NAND followed, partly because the capex committees that paused NAND investment in 2023 are now watching the consequences land all at once.

Hyperscalers absorb it on contract without complaint. Consumer OEMs absorb it on margin, and price flows straight to the shelf.

Why it shows up in the Fed's data now

Three things had to line up for this to register in the inflation print.

First, the upstream PPI had to break out of its decade-long disinflation channel. Plus one hundred and fifty six is not a small number. It is the largest print in the history of this series.

Second, downstream categories had to absorb enough that the move could not be hidden inside inventory. Storage started lifting in October 2025. Software and accessories followed in January 2026. The lag is about four months.

Third, the core PCE weight had to be heavy enough to push the headline. Software and accessories is roughly half a percent of core PCE. Fourteen percent year on year at that weight is seven basis points on its own. Stack it with adjacent categories doing similar things and it becomes a Fed problem.

Why this is not transitory

New DRAM fab capacity takes three to four years to break ground, install, and qualify. The CoWoS packaging step that turns DRAM stacks into HBM is even tighter, and TSMC is the bottleneck. TSMC has been clear that 2027 is the earliest meaningful capacity addition.

Until then, the share of wafers going to HBM rises every quarter and the share going to ordinary DRAM falls. The supply chain is not broken. It is being redirected, deliberately, into a higher-margin product. The redirect is rational. It is also one-directional.

What to watch from here

None of these has fired. The earliest credible date for any of them is mid to late 2026. Until then, the chart at the top keeps doing what it is doing.

Memory is now an inflation category, not just a technology category. The Fed knows it. The minutes will say it before the press conference does. The carry is in front-running the data.

Hero chart: Inflation Insights LLC, via @TheStalwart on X, May 20 2026. Source data: BEA, BLS, Haver Analytics.